As the size of active impurity regions in semiconductor integrated circuit substrates shrink the size of the electrical contacts to those regions likewise shrink. A limiting factor is the minimum line that can be produced in a given technology. When the impurity region is reduced to that minimum dimension the contact "window" that is made prior to forming the contact cannot, as is customary, be made smaller than the region to be contacted. As a result both features are made with the minimum feature size and the contact will almost certainly be partially non-aligned or offset with the region to be contacted. This situation is commonly referred to as "line-on-line" features, i.e. features that require minimum line on minimum line registration. Whether the alignment is visual or automatic it is not possible to make precise line-on-line features.
This difficulty can be overcome by implanting an appropriate impurity into the contact window prior to forming the contact. This produces a self-aligned contact with the region to be contacted.
As useful as this tool evidently is, it suffers when applied to CMOS technology. In that case two implants and additional masks are required because p-type impurities are required for the p-channel device windows and n-type impurities for the n-channel device windows.
A need remains for a technique for producing line-on-line contacts that can be applied to CMOS as well as other technologies.